A/D Control/Status Register (Adcsr) - Renesas H8S/2100 Series Hardware Manual

Table 22.3 Analog Input Channels and Corresponding ADDR
Analog Input Channel
Channel Set 0 (CH3 = 0)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
22.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D converter operation.
Bit Bit Name Initial Value
7 ADF 0
6 ADIE 0
Channel Set 1 (CH3 = 1)
AN8
AN9
AN10
AN11




R/W Description
R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends on all channels
specified in scan mode
[Clearing condition]
•
When 0 is written after reading ADF = 1
R/W A/D Interrupt Enable
Enables ADI interrupt by ADF when this bit is set to 1.
Section 22 A/D Converter
A/D Data Register to Store A/D
Conversion Results
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
Rev. 1.00 May 09, 2008 Page 697 of 954
REJ09B0462-0100