Renesas H8S/2100 Series Hardware Manual page 482

6-bit single-chip microcomputer

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Table of Contents

Section 16 Serial Communication Interface with FIFO (SCIF)

Figure 16.1 shows a block diagram of the SCIF.

System clock

Receive shift register

Transmitter shift register

Receive buffer register

Transmitter holding register

FDLH, FDLL: Divisor latch H, L

Interrupt enable register

Interrupt identification register

Rev. 1.00 May 09, 2008 Page 456 of 954

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transmission/

SCIFCR: SCIF control register

Figure 16.1 Block Diagram of SCIF

Transmit FIFO

Transmission

Receive FIFO

Transfer clock

FIFO control register

Line control register

Modem control register

Line status register

Modem status register

Scratch pad register