Data Transmission/Reception Through The Lpc Interface - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Data Transmission/Reception Through the LPC Interface

As shown in table 16.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to

be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the

SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception

shown in figures 16.3 to 16.5 to be made from the LPC interface. Table 16.7 shows the

correspondence between LPC interface I/O address and access to the SCIF registers. For details of

the LPC interface settings, see section 20, LPC interface (LPC).

Table 16.7 Correspondence Between LPC Interface I/O Address and the SCIF Registers

LPC Interface I/O Address

Bits 15 to 3

SCIFADR (bits 15 to 3)

Section 16 Serial Communication Interface with FIFO (SCIF)

Rev. 1.00 May 09, 2008 Page 487 of 954

REJ09B0462-0100