Table of Contents
Advertisement
Section 8 I/O Ports
(4)
P44/TMO1/PWMU2B/TCMCYI2
The pin function is switched as shown below according to the combination of the OS3 to OS0 bits
in TCR of TMR_1, the PWM2E bit in PWMOUTCR of PWMU_B, and the P44DDR bit. When
the TCMIPE bit in TCMIER_2 of TCM_2 is set to 1, the pin functions as the TCMCY2 input pin.
OS3 to OS0
P44DDR
PWM2E
Pin function
(5)
P43/TMI1/TCMCKI1/TCMMCI1
The pin function is switched as shown below according to the P43DDR bit. TMRI1 and TMCI1
are multiplexed as the TMI1 input pin. When the CCLR1 and CCLR0 bits in TCR of TMR_1 are
set to 1, the pin functions as the TMI1 (TMRI1) input pin. When an external clock is selected by
the CKS2 to CKS0 bits in TCR of TMR_1, the pin functions as the TMI1 (TMCI1) input pin.
When an external clock is selected by the CKS2 to CKS0 bits in TCMCR of TCM_1, the pin
functions as the TCMCKI1 input pin. When the CMMS bit in TCMIER of TCM_1 is set to 1, the
pin functions as the TCMMCI1 input pin.
P43DDR
Pin function
(6)
P42/TCMCYI1
The pin function is switched as shown below according to the P42DDR bit. When the TCMIPE bit
in TCMIER_1 of TCM_1 is set to 1, the pin functions as the TCMCYI1 input pin.
P42DDR
Pin function
Rev. 1.00 May 09, 2008 Page 168 of 954
REJ09B0462-0100
0
P44 input pin
P44 output pin
0
P43 input pin
TMI1 input pin/TCMCKI1 input pin/TCMMCI1 input pin
0
P42 input pin
All 0
1
0
PWMU2B
output pin
TCMCYI2 input pin
TCMCYI1 input pin
Any of them is 1
1
TM01 output pin
1
P43 output pin
1
P42 output pin
Advertisement
Table of Contents
