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Internal register
H'67_45_23_01
FSIAR[23:0]
H'06_4A_70
FSIRDINS[7:0]
H'03
LCLK
LFRAME
LAD[3:0]
ST CT
ADDR
φ
FSIAR[23:0]
FSIRDINS[7:0]
FSICR2 RE bit
FSITDR7 to
FSITDR0
FSISTR FSIRXI bit
FSIRDR3 to
FSIRDR0
FSISS
FSICK (CPOS = CPHS =0)
FSIDO
FSIDI
FSIAR[7:0]
FSIAR[15:8]
FSIAR[23:16]
Figure 21.8 Data Transfer to FSIRDR (Example)
TAR
Figure 21.9 Read Instruction Execution Timing
FSITDR3
H'70
H'4A
H'06
H'03
FSITDR0
FSIDI
WAIT
H'03
H'70-4A-06-03
H'02->06->4A->70
H'01->23->45->67
Rev. 1.00 May 09, 2008 Page 679 of 954
Section 21 FSI Interface
First receive data
H'01
Second receive data
H'23
Third receive data
H'45
Fourth receive data
H'67
FSISFR
SY
DATA
H'06-4A-70
H'01->23->45->67
REJ09B0462-0100
FSIRDR3
FSIRDR0
FSIDO
TAR
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