Table of Contents
Advertisement
Initial
Bit
Bit Name
Value
2
CKS2
0
1
CKS1
0
0
0
CKS0
Note:
1. Only 0 can be written to clear the flag.
2. When OVF is polled with the interval timer interrupt disabled, OVF = 1 must be read at
least twice.
4.4
Pin Reset
This is a reset generated by the RES pin.
When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a
reset state. In order to firmly reset the LSI by pin reset, the RES pin should be held low at least for
20 ms at a power-on. When a reset is input during operation, the RES pin should be held low at
least for 20 states. Resetting the LSI initializes the internal state of the CPU and the registers of the
on-chip peripheral modules.
R/W
Description
R/W
Clock Select 2 to 0
R/W
Selects the clock source to be input to TCNT. The overflow
frequency for φ = 20 MHz and φSUB = 32.768 kHz is
R/W
enclosed in parentheses.
When PSS = 0
000: φ/2 (frequency: 25.6 µs)
001: φ/64 (frequency: 819.2 µs)
010: φ/128 (frequency: 1.6 µs)
011: φ/512 (frequency: 6.6 µs)
100: φ/2048 (frequency: 26.2 µs)
101: φ/8192 (frequency: 104.9 µs)
110: φ/32768 (frequency: 419.4 µs)
111: φ/131072 (frequency: 1.68 s)
When PSS = 1
000: φSUB/2 (frequency: 16.5ms)
001: φSUB/4 (frequency: 31.3ms)
010: φSUB/8 (frequency: 62.5ms)
011: φSUB/16 (frequency: 125ms)
100: φSUB/32 (frequency: 250ms)
101: φSUB/64 (frequency: 500ms)
110: φSUB/128 (frequency: 1s)
111: φSUB/256 (frequency: 2s)
Section 4 Resets
Rev. 1.00 May 09, 2008 Page 83 of 954
REJ09B0462-0100
Advertisement
Table of Contents
