21.3.5
FSI Instruction Register (FSIRDINS)
FSIRDINS sets a read operation instruction to be sent to FSITDR during read operation. When
LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register should be
modified during initialization.
Bit
Bit Name
7 to 0 bit 7 to bit 0 All 0
21.3.6
FSI Program Instruction Register (FSIPPINS)
FSIPPINS sets a program operation instruction to be sent to FSITDR during program operation.
When LFBUSY is set to 1, a write to this register by the EC (this LSI) is invalid. This register
should be modified during initialization.
Bit
Bit Name
7 to 0 bit 7 to bit 0 All 0
21.3.7
FSI Status Register (FSISTR)
FSISTR indicates the processing status of the EC (this LSI) and the SPI flash memory transfer.
Initial
Bit
Bit Name
Value
7
FSITEI
0
R/W
Initial
Value
EC
Host Description
R/W
R/W
Initial
Value
EC
Host Description
R/W
R/W
EC
Host
R/(W)*
These bits store a read operation instruction.
These bits store a program operation instruction.
Description
FSI Transmit End Interrupt Flag
[Setting condition]
When write data has been transmitted to the SPI
flash memory.
[Clearing condition]
When this bit is read as 1 and then written with 0.
Rev. 1.00 May 09, 2008 Page 657 of 954
Section 21 FSI Interface
REJ09B0462-0100