Spi Flash Memory Transfer - Renesas H8S/2100 Series Hardware Manual

6-bit single-chip microcomputer

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Table of Contents

Section 21 FSI Interface

FW Memory Read Cycles

Counts Content

The number of wait cycles depends on the system clock.

The FSI supports byte, word, and longword transfers of FW memory read and write cycles. In

word transfer, the least address bit is fixed to B'0; while in longword transfer, the lower 2 bits are

fixed to B'00. When longword transfers of FW memory write cycles are used, the maximum

operating frequency of the system clock is 10 MHz.

SPI Flash Memory Transfer

The SPI flash memory transfer is performed using FSIDO and FSIDI synchronously with FSICK.

The initial value of FSICK can be either fixed to high or low through programming.

Rev. 1.00 May 09, 2008 Page 672 of 954

REJ09B0462-0100

Value (3 to 0)

Figure 21.2 Example of SPI Flash Memory Transfer

FW Memory Write Cycles

Driven by Value (3 to 0)