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Section 20 LPC Interface (LPC)
Register Name
Bidirectional data register 0MW
Bidirectional data register 0SW
Bidirectional data register 1
Bidirectional data register 2
Bidirectional data register 3
Bidirectional data register 4
Bidirectional data register 5
Bidirectional data register 6
Bidirectional data register 7
Bidirectional data register 8
Bidirectional data register 9
Bidirectional data register 10
Bidirectional data register 11
Bidirectional data register 12
Bidirectional data register 13
Bidirectional data register 14
Bidirectional data register 15
SERIRQ control register 0
SERIRQ control register 1
SERIRQ control register 2
SERIRQ control register 3
SERIRQ control register 4
Host interface select register
SCIF address register H
SCIF address register L
Notes: R/W in the register description means as follows:
1. R/W slave indicates access from the slave (this LSI).
2. R/W host indicates access from the host.
Rev. 1.00 May 09, 2008 Page 586 of 954
REJ09B0462-0100
R/W
Abbreviation Slave Host
TWR0MW
R/W
TWR0SW
R/W
TWR1
R/W
TWR2
R/W
TWR3
R/W
TWR4
R/W
TWR5
R/W
TWR6
R/W
TWR7
R/W
TWR8
R/W
TWR9
R/W
TWR10
R/W
TWR11
R/W
TWR12
R/W
TWR13
R/W
TWR14
R/W
TWR15
R/W
SIRQCR0
R/W
SIRQCR1
R/W
SIRQCR2
R/W
SIRQCR3
R/W
SIRQCR4
R/W
HISEL
R/W
SCIFADRH
R/W
SCIFADRL
R/W
Initial
Value Address
R/W
H'00
H'FE20
R/W
H'00
H'FE20
R/W
H'00
H'FE21
R/W
H'00
H'FE22
R/W
H'00
H'FE23
R/W
H'00
H'FE24
R/W
H'00
H'FE25
R/W
H'00
H'FE26
R/W
H'00
H'FE27
R/W
H'00
H'FE28
R/W
H'00
H'FE29
R/W
H'00
H'FE2A
R/W
H'00
H'FE2B
R/W
H'00
H'FE2C
R/W
H'00
H'FE2D
R/W
H'00
H'FE2E
R/W
H'00
H'FE2F
H'00
H'FE36
H'00
H'FE37
H'00
H'FDDA
H'00
H'FDDB
H'00
H'FE3B
H'03
H'FE3F
H'03
H'FDC4
H'F8
H'FDC5
Data Bus
Width
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
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