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11.6
Usage Notes
11.6.1
Conflict between TCMCNT Write and Count-Up Operation
When a conflict between TCMCNT write and count-up operation occurs in the second half of the
TCMCNT write cycle, TCMCNT is not incremented and writing to TCMCNT takes priority.
Figure 11.13 shows the timing of this conflict.
φ
Internal write
signal
Internal clock
TCMCNT
input clock
TCMCNT
Figure 11.13 Conflict between TCMCNT Write and Count-Up Operation
11.6.2
Conflict between TCMMLCM Write and Compare Match
When a conflict between TCMMLCM write and a compare match should occur in the second half
of a cycle of writing to TCMMLCM, writing to TCMMLCM takes priority and the compare
match signal is inhibited. Figure 11.14 shows the timing of this conflict.
φ
Internal write
signal
TCMCNT
TCMMLCM
Compare match
signal
Figure 11.14 Conflict between TCMMLCM Write and Compare Match
Section 11 16-Bit Cycle Measurement Timer (TCM)
T1
T2
N - 1
T1
T2
N
N
N
N + 1
M
Inhibited
Rev. 1.00 May 09, 2008 Page 311 of 954
N + 1
N + 2
REJ09B0462-0100
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