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Section 10 16-Bit Timer Pulse Unit (TPU)
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figure 10.42 shows the
timing for status flag clearing by the CPU.
φ
Address
Write signal
Status flag
Interrupt
request signal
Figure 10.42 Timing for Status Flag Clearing by CPU
Rev. 1.00 May 09, 2008 Page 282 of 954
REJ09B0462-0100
TSR write cycle
T1
T2
TSR address
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