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Section 15 CIR Interface
15.8
Usage Note
(1)
CIR Register Setting
Before starting the CIR reception, set the CIR by following the flow shown in figure 15.7.
The CPHS bit in CCR1 should be set before starting reception. When the CIRI pin is high in the
idle state, set the CPHS bit to 1. When it is low in the idle state, clear the bit to 0. The BRR
register is initialized to H'FF by setting the SRES bit in CCR1 to 1. After setting each register in
the CIR, set the CIRE bit in CCR1 to 1 to enable the CIR reception.
(2)
Switching between System Clock and Sub Clock
The CIR is capable of remote-control reception by using the sub clock in watch mode. Before
switching between the system clock and the sub clock, the CIR must be stopped by clearing the
CIRE bit to 0.
Rev. 1.00 May 09, 2008 Page 452 of 954
REJ09B0462-0100
Start of setting
Clear MSTPA3 bit in MSTPCRA to 0.
Set CPHS bit in CCR1.
Set each register.
Clear CSTR flag.
Set CEIR.
Set CIRE bit in CCR1 to 1.
End of setting
Figure 15.9 CIR Setting Flow
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