Renesas H8S/2100 Series Hardware Manual page 609

6-bit single-chip microcomputer

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Table of Contents

Figure 20.1 shows a block diagram of the LPC.

Cycle detection

Serial → parallel conversion

Serial ← parallel conversion

Cycle detection

HICR0 to HICR5:

Host interface control registers 0 to 5

LADR1H/L to 4H/L:

LPC channel 1 to 4 address registers

SCIF address register H and L

IDR1 to IDR4:

Input data registers 1 to 4

ODR1 to ODR4:

Output data registers 1 to 4

Module data bus

Address match

Figure 20.1 Block Diagram of LPC

Section 20 LPC Interface (LPC)

Parallel → serial conversion

SIRQCR0 to 4

Control logic

HICR0 to HICR5

Internal interrupt

STR1 to STR4:

Status registers 1 to 4

Bidirectional data register 0MW

Bidirectional data register 0SW

TWR1 to TWR15:

Bidirectional data registers 1 to 15

SIRQCR0 to SIRQCR4:

SERIRQ control registers 0 to 4

Host interface select register

Rev. 1.00 May 09, 2008 Page 583 of 954

REJ09B0462-0100