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20.3.4
Host Interface Control Register 5 (HICR5)
HICR5 enables or disables the operation of the SCIF interface, and controls OBEI interrupts.
Initial
Bit
Bit Name
Value
7
OBEIE
0
6
OBEI
0
5 to 4
All 0
3
SCIFE
0
2 to 0
All 0
R/W
Slave Host Description
R/W
Output Buffer Empty Interrupt Enable
Enables or disables OBEI interrupts (for this LSI).
0: Output buffer empty interrupt request is disabled
1: Output buffer empty interrupt request is enabled
R/W
Output Buffer Empty Interrupt Flag
0: [Clearing conditions]
•
Writing 0 after reading OBEI = 1
•
LPC hardware reset or LPC software reset
1: [Setting condition]
When one of OBF1, OBF2, OBF3A, OBF3B,
and OBF4 is cleared
R/W
Reserved
The initial value should not be changed.
R/W
SCIF Enable
Enables or disables access from the LPC host of
the SCIF.
0: Disables access from the LPC host of the SCIF
1: Enables access from the LPC host of the SCIF
R/W
Reserved
The initial value should not be changed.
Section 20 LPC Interface (LPC)
Rev. 1.00 May 09, 2008 Page 597 of 954
REJ09B0462-0100
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