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Section 26 Power-Down Modes
26.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in
TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules,
and clock pulse generator all stop. However, the contents of the CPU registers and some of the on-
chip peripheral registers, and on-chip RAM data are retained as long as the prescribed voltage is
supplied. Also, the I/O port retains the state before transition to the software standby mode.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15, KIN0 to KIN15,
or WUE0 to WUE15), PS2 interrupt, or RES pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When clearing software standby mode with an IRQ0 to
IRQ15 interrupt, set the corresponding enable bit to 1. When clearing software standby mode with
a KIN0 to KIN15 or WUE0 to WUE15 interrupt, enable the input. In these cases, ensure that no
interrupt with a higher priority than interrupts IRQ0 to IRQ15 is generated. In the case of an IRQ0
to IRQ15 interrupt, software standby mode is not cleared if the corresponding enable bit is cleared
to 0 or if the interrupt has been masked by the CPU. In the case of a KIN0 to KIN15 or WUE0 to
WUE15 interrupt, software standby mode is not cleared if the input is disabled or if the interrupt
has been masked by the CPU.
When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with
the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the
RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after
the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling.
Figure 26.3 shows an example in which a transition is made to software standby mode at the
falling edge of the NMI pin, and software standby mode is cleared at the rising edge of the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge of the NMI pin.
Rev. 1.00 May 09, 2008 Page 821 of 954
REJ09B0462-0100
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