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27.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Port 1 data direction register
Port 2 data direction register
Port 1 data register
Port 2 data register
Port 1 input data register
Port 2 input data register
Port 1 pull-up MOS control
register
Port 2 pull-up MOS control
register
Port 3 data direction register
Port 4 data direction register
Port 3 data register
Port 4 data register
Port 3 input data register
Port 4 input data register
Port 3 pull-up MOS control
register
Number
Abbreviation
of bits
P1DDR
8
P2DDR
8
P1DR
8
P2DR
8
P1PIN
8
P2PIN
8
P1PCR
8
P2PCR
8
P3DDR
8
P4DDR
8
P3DR
8
P4DR
8
P3PIN
8
P4PIN
8
P3PCR
8
Section 27 List of Registers
Address
Module
H'F900
PORT
(PORTS = 1)
H'F901
PORT
(PORTS = 1)
H'F902
PORT
(PORTS = 1)
H'F903
PORT
(PORTS = 1)
H'F904 (Read)
PORT
(PORTS = 1)
H'F905 (Read)
PORT
(PORTS = 1)
H'F906
PORT
(PORTS = 1)
H'F907
PORT
(PORTS = 1)
H'F910
PORT
(PORTS = 1)
H'F911
PORT
(PORTS = 1)
H'F912
PORT
(PORTS = 1)
H'F913
PORT
(PORTS = 1)
H'F914 (Read)
PORT
(PORTS = 1)
H'F915 (Read)
PORT
(PORTS = 1)
H'F916
PORT
(PORTS = 1)
Rev. 1.00 May 09, 2008 Page 827 of 954
Data
Access
Width
States
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
REJ09B0462-0100
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