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Section 8 I/O Ports
8.2.7
Port 7
(1)
P77/AN7, P76/AN6, P75/AN5, P74/AN4, P73/AN3, P72/AN2, P71/AN1, P70/AN0
Pin function
8.2.8
Port 8
(1)
P86/IRQ5/SCK1
The pin function is switched as shown below according to the combination of the C/A bit in SMR
and the CKE0 and CKE1 bits in SCR of SCI_1, and the P86DDR bit. When the ISS5 bit in ISSR
is cleared to 0 and the IRQ5E bit in IER of the interrupt controller is set to 1, this pin functions as
the IRQ5 input pin.
CKE1
C/A
CKE0
P86DDR
Pin function
(2)
P85/IRQ4/RxD1
The pin function is switched as shown below according to the combination of the RE bit in SCR
of SCI_1and the P85DDR bit. When the ISS4 bit in ISSR is cleared to 0 and the IRQ4E bit in IER
of the interrupt controller is set to 1, this pin functions as the IRQ4 input pin.
RE
P85DDR
Pin function
Rev. 1.00 May 09, 2008 Page 172 of 954
REJ09B0462-0100
0
0
0
1
P86 input
P86 output
pin
pin
0
P85 input pin
ANn/P7n input
0
1
SCK1
output pin
IRQ5 input pin
0
1
P85 output pin
IRQ4 input pin
(n = 7 to 0)
1
1
SCK1
SCK1 input
output pin
pin
1
RxD1 input pin
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