Renesas H8S/2100 Series Hardware Manual page 350

Section 12 8-Bit Timer (TMR)
Channel CKS2 CKS1
Common 1 0
1 1
1 1
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
Table 12.3 Clock Input to TCNT and Count Condition (2)
Channel CKS2 CKS1
TMR_Y 0 0
0 0
0 1
0 1
1 0
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Rev. 1.00 May 09, 2008 Page 324 of 954
REJ09B0462-0100
TCR
CKS0 ICKS1
1 —
0 —
1 —
TCR
CKS0 CKSX
0 —
1 —
0 —
1 —
0 —
0 —
1 —
0 —
1 —
0 —
1 —
0 —
1 —
STCR
ICKS0 Description
— Increments at rising edge of external
clock
— Increments at falling edge of external
clock
— Increments at both rising and falling
edges of external clock
TCRXY
CKSY Description
0 Disables clock input
Increments at φ/4
0
Increments at φ/256
0
Increments at φ/2048
0
0 Disables clock input
1 Disables clock input
Increments at φ/4096
1
Increments at φ/8192
1
Increments at φ/16384
1
1 Increments at overflow signal from
TCNT_X*
x Increments at rising edge of external
clock
x Increments at falling edge of external
clock
x Increments at both rising and falling
edges of external clock