MST
TRS
BBSY ESTP
0
0
1
0
0
0
1
0
0
0
1
0
0
—
0↓
1↑/0
(*
[Legend]
0:
0-state retained
1:
1-state retained
—:
Previous state retained
0
↓
:
Cleared to 0
1
↑
:
Set to 1
Notes: 1. Set to 1 when 1 is received as a R/W bit following an address.
2. Set to 1 when the AASX bit is set to 1.
3. When ESTP=1, STOP is 0, or when STOP=1, ESTP is 0.
STOP
IRTR
AASX AL
0
—
—
0
—
—
0
1↑/0
—
2
(*
)
0/1↑
—
—
3
3
)
(*
)
AAS
ADZ
ACKB ICDRF ICDRE State
—
—
—
—
0↓
0↓
0↓
—
0
0
0
—
—
—
—
—
Rev. 1.00 May 09, 2008 Page 511 of 954
2
Section 17 I
C Bus Interface (IIC)
1
—
Reception end
with ICDRF=1
0↓
—
ICDR read
with the above
state
1↑
—
Automatic
data transfer
from ICDRS to
ICDRR with
the above
state
—
0↓
Stop condition
detected
REJ09B0462-0100