Renesas H8S/2100 Series Hardware Manual page 12

6.8.4 Vector Address Switching .................................................................................... 144
6.8.5 External Interrupt Pin in Software Standby Mode and Watch Mode.................... 145
6.8.6 Noise Canceler Switching..................................................................................... 145
6.8.7 IRQ Status Register (ISR)..................................................................................... 145
Section 7 Bus Controller (BSC) ........................................................................147
7.1 Register Descriptions ......................................................................................................... 147
7.1.1 Bus Control Register (BCR) ................................................................................. 147
7.1.2 Wait State Control Register (WSCR) ................................................................... 148
Section 8 I/O Ports............................................................................................. 149
8.1 Register Descriptions ......................................................................................................... 156
8.1.1 Data Direction Register (PnDDR) (n = 1 to 6, 8, 9, A to D, and F to H).............. 157
8.1.2 Data Register (PnDR) (n = 1 to 6, 8, and 9).......................................................... 158
8.1.3 Input Data Register (PnPIN) (n = 1 to 9 and A to J)............................................. 158
8.1.4 Pull-Up MOS Control Register (PnPCR) (n = 1 to 3, 6, 9, B to D, F, and H) ...... 159
Output Data Register (PnODR) (n = A to D and F to H)...................................... 160
8.1.5
Noise Canceler Enable Register (PnNCE) (n = 4, 6, C, and G)............................ 161
8.1.6
Noise Canceler Decision Control Register (PnNCMC) (n = 4, 6, C, and G)........ 161
8.1.7
Noise Cancel Cycle Setting Register (PnNCCS) (n = 4, 6, C, and G) .................. 162
8.1.8
Port Nch-OD Control Register (PnNOCR) (n = C, D, F, G, and H)..................... 163
8.1.9
8.1.10 MOS State of Output Buffer ................................................................................. 164
8.2 Pin Functions ..................................................................................................................... 165
8.2.1 Port 1..................................................................................................................... 165
8.2.2 Port 2..................................................................................................................... 165
8.2.3 Port 3..................................................................................................................... 166
8.2.4 Port 4..................................................................................................................... 167
8.2.5 Port 5..................................................................................................................... 170
8.2.6 Port 6..................................................................................................................... 171
8.2.7 Port 7..................................................................................................................... 172
8.2.8 Port 8..................................................................................................................... 172
8.2.9 Port 9..................................................................................................................... 175
8.2.10 Port A.................................................................................................................... 176
8.2.11 Port B.................................................................................................................... 177
8.2.12 Port C.................................................................................................................... 180
8.2.13 Port D.................................................................................................................... 184
8.2.14 Port E .................................................................................................................... 185
8.2.15 Port F .................................................................................................................... 186
8.2.16 Port G.................................................................................................................... 188
8.2.17 Port H.................................................................................................................... 192
Rev. 1.00 May 09, 2008 Page xii of xxvi