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22.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit
Bit Name Initial Value
7
TRGS1
0
6
TRGS0
0
5
SCANE
0
4
SCANS
0
3
CKS1
0
2
CKS0
0
1
ADSTCLR 0
R/W
Description
R/W
Timer Trigger Select 1 and 0
R/W
Enable the start of A/D conversion by a trigger signal.
00: A/D conversion start by external trigger is disabled
01: A/D conversion start by conversion trigger from
TPU
10: A/D conversion start by conversion trigger from
TMR
11: Setting prohibited
R/W
Scan Mode
R/W
Select the A/D conversion operating mode.
0x: Single mode
10: Scan mode
Continuous A/D conversion on 1 to 4 channels
11: Scan mode
Continuous A/D conversion on 1 to 8 channels
R/W
Clock Select 1 and 0
R/W
These bits select the clock (ADCLK)* used in A/D
conversion. Set these bits while the ADST bit in
ADCSR is 0, then set the conversion mode.
00: φ
01: φ/2
10: φ/4
00: φ/8
R/W
A/D Start Clear
Sets the automatic clearing of the ADST bit in scan
mode.
0: Disables the automatic clearing of the ADST bit in
scan mode
1: Automatically clears the bit when A/D conversion of
all of the selected channels are completed
Section 22 A/D Converter
Rev. 1.00 May 09, 2008 Page 699 of 954
REJ09B0462-0100
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