ST STM32L4+ Series Reference Manual page 1311

RM0432
The following figures show some examples of the counter behavior for different clock
frequencies when TIMx_ARR=0x36.
Timerclock = CK_CNT
Counter register
Counter underflow
(cnt_udf)
Update event (UEV)
Update interrupt flag
Timerclock = CK_CNT
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
Figure 353. Counter timing diagram, internal clock divided by 1
CK_PSC
CNT_EN
05
(UIF)
Figure 354. Counter timing diagram, internal clock divided by 2
CK_PSC
CNT_EN
0002
(UIF)
RM0432 Rev 6
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
04
02 01 00 36
03
0000
0001
35 34 33 32
31
0036 0035 0034
30 2F
MS31184V1
0033
MS31185V1
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