Interrupt Request; Bit Synchronous Circuit; Figure 15.18 Timing Of The Bit Synchronous Circuit; Table 15.3 Interrupt Requests - Renesas H8S/2368 Series Hardware Manual

15.5

Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost. Table 15.3 shows the contents of each
interrupt request.

Table 15.3 Interrupt Requests

Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Detection
Arbitration Lost
15.6

Bit Synchronous Circuit

In master mode,
• When SCL is driven to low by the slave device
• When the rising speed of SCL is lower by the load of the SCL line (load capacitance or pull-up
resistance)
This module has a possibility that high level period may be short in the two states described
above. Therefore it monitors SCL and communicates by bit with synchronization.
Figure 15.18 shows the timing of the bit synchronous circuit and table 15.4 shows the time when
SCL output changes from low to Hi-Z then SCL is monitored.
SCL monitor
timing reference
clock
SCL
Internal SCL
Rev. 2.00, 05/03, page 616 of 820
Abbreviation
TXI
TEI
RXI
STPI
NAKI

Figure 15.18 Timing of the Bit Synchronous Circuit

Interrupt Condition
(TDRE=1) (TIE=1)
•
(TEND=1) (TEIE=1)
•
(RDRF=1) (RIE=1)
•
(STOP=1) (STIE=1)
•
{(NACKF=1)+(AL=1)}
VIH
(NAKIE=1)
•