Interrupt Requests; Table 14.7 Interrupt Sources - Renesas H8SX/1520 Series Hardware Manual

14.5

Interrupt Requests

The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts. Of these interrupt sources, a receive
data register full, a transmit data register empty, and a transmit end interrupts can activate the
DMAC for data transfer.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 14.7 lists the
interrupt sources.
When an interrupt condition shown in table 14.7 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DMAC data transfer.

Table 14.7 Interrupt Sources

Channel Abbreviation Interrupt Source
0 SSERI0
SSRXI0
SSTXI0
1 SSERI1
SSRXI1
SSTXI1
2 SSERI2
SSRXI2
SSTXI2
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Overrun error
Conflict error
Receive data register full
Transmit data register empty
Transmit end
Overrun error
Conflict error
Receive data register full
Transmit data register empty
Transmit end
Overrun error
Conflict error
Receive data register full
Transmit data register empty
Transmit end
Section 14 Synchronous Serial Communication Unit (SSU)
Symbol Interrupt Condition
(RIE = 1) • (ORER = 1)
OEI0
(CEIE = 1) • (CE = 1)
CEI0
(RIE = 1) • (RDRF = 1)
RXI0
(TIE = 1) • (TDRE = 1)
TXI0
(TEIE = 1) • (TEND = 1)
TEI0
(RIE = 1) • (ORER = 1)
OEI1
(CEIE = 1) • (CE = 1)
CEI1
(RIE = 1) • (RDRF = 1)
RXI1
(TIE = 1) • (TDRE = 1)
TXI1
(TEIE = 1) • (TEND = 1)
TEI1
(RIE = 1) • (ORER = 1)
OEI2
(CEIE = 1) • (CE = 1)
CEI2
(RIE = 1) • (RDRF = 1)
RXI2
(TIE = 1) • (TDRE = 1)
TXI2
(TEIE = 1) • (TEND = 1)
TEI2
Rev. 3.00 Mar. 14, 2006 Page 545 of 804
DMAC
Activation


Yes
Yes
Yes


Yes
Yes
Yes


Yes
Yes
Yes
REJ09B0104-0300