Clock Synchronous Communication Mode; Figure 14.12 Example Of Initial Settings In Clock Synchronous Communication Mode - Renesas H8SX/1520 Series Hardware Manual

14.4.7

Clock Synchronous Communication Mode

In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Initial Settings in Clock Synchronous Communication Mode
Figure 14.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
[1]
[2]
[3]
[4]
[5]

Figure 14.12 Example of Initial Settings in Clock Synchronous Communication Mode

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Start setting initial values
Clear TE and RE bits in SSER to 0
Set a bit in ICR to 1
Specify MSS and SCKS in SSCRH
Set SSUMS in SSCRL to 1 and
specify bits DATS1 and DATS0
Specify CPOS, CKS2, CKS1, and
CKS0 bits in SSMR
Specify SDOS, SSCKOS, SCSOS,
TENDSTS, SCSATS, and
SSODTS bits in SSCR2
Specify TE, RE, TEIE, TIE, RIE, and
CEIE bits in SSER simultaneously
End
Section 14 Synchronous Serial Communication Unit (SSU)
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
selection.
[3] Selects clock synchronous communication mode and
specify transmit/receive data length.
[4] Specify clock polarity selection and transfer clock rate
selection.
[5] Enables/disables interrupt request to the CPU.
Rev. 3.00 Mar. 14, 2006 Page 539 of 804
REJ09B0104-0300