Clock Synchronous Serial I/O Mode - Renesas M16C/60 Series Hardware Manual

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M16C/6N5 Group

Clock Synchronous Serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 1.15.1
lists the specifications of the clock synchronous serial I/O mode. Table 1.15.2 lists the registers used in
clock synchronous serial I/O mode and the register values set.
Table 1.15.1 Clock Synchronous Serial I/O Mode Specifications
Item
Transfer data format
Transfer clock
Transmission, reception control
Transmission start condition
Reception start condition
Interrupt request
generation timing
Error detection
Select function
i = 0 to 2
Note 1: When an external clock is selected, the conditions must be met while if the UiC0 register's CKPOL bit = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the UiC0 register's CKPOL bit = 1 (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
Note 2: The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.
Note 3: If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit of SiRIC register does not change.
Rev.1.00 2003.05.30 page 142
• Transfer data length: 8 bits
• UiMR register's CKDIR bit = 0 (internal clock) : fj/ 2(n+1)
fj = f , f , f , f . n: Setting value of UiBRG register
1SIO 2SIO 8SIO 32SIO
• CKDIR bit = 1 (external clock ) : Input from CLKi pin
_______
• Selectable from CTS function, RTS function or CTS/RTS function disabled
• Before transmission can start, the following requirements must be met (Note 1)
_
The TE bit of UiC1 register = 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in UiTB register)
_______
_
If CTS function is selected, input on the CTSi pin = L
• Before reception can start, the following requirements must be met (Note 1)
_
The RE bit of UiC1 register = 1 (reception enabled)
_
The TE bit of UiC1 register = 1 (transmission enabled)
_
The TI bit of UiC1 register = 0 (data present in the UiTB register)
• For transmission, one of the following conditions can be selected
_
The UiIRS bit (Note 2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
_
The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
• For reception
When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
• Overrun error (Note 3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
_______ _______
• Separate CTS/RTS pins (UART0)
_________ _________
CTS and RTS are input/output from separate pins
0 0
Serial I/O (Clock Synchronous Serial I/O Mode)
Specification
_______ _______ _______
_______
00 to FF
16 16