Mixing 32-Bit & 48-Bit Words In One Memory Block - Analog Devices ADSP-2106x SHARC User Manual

ADSP-21061 (Two blocks of 4Kx16-bit columns)
Block 0
|--------------|--------------|---------|
48-bit
| H | M | L | L
words
|--------------|--------------|---------|
0x20000 0x21000
|---------|---------|---------|---------|
32/16-bit
| H | L | H | L
words
|---------|---------|---------|---------|
0x20000 0x21000
Block 1
|--------------|--------------|---------|
48-bit
| H | M | L | L
words
|--------------|--------------|---------|
0x24000 0x25000
|---------|---------|---------|---------|
32/16-bit
| H | L | H | L
words
|---------|---------|---------|---------|
0x24000 0x25000
Figure 5.9b Memory Organization vs. Address (ADSP-21061)
Note: All addresses denote the first location of each column.
5.3.2 Mixing 32-Bit & 48-Bit Words In One Memory Block
32-bit data words and 48-bit instruction words can be stored in the
same memory block, with the restriction that all instructions must reside
at addresses lower than the data. No instruction may be stored at an
address higher than the lowest address of any data word. This
restriction is necessary to prevent addresses for 32-bit words and 48-bit
words from overlapping.
The rules for combining 48-bit instruction words and 32-bit data words
within the same block of memory are as follows:
• Instruction storage must start at the lowest address in the block.
• Data storage must start on an even column number
• All data must be located at addresses higher than all instructions
• Instructions require three contiguous 16-bit columns
• Data words require two contiguous 16-bit columns
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Memory
| H | M | |
0x22000 |
| H | L | H | L |
0x22000 0x23000 |
| H | M | |
0x26000 |
| H | L | H | L |
0x26000 0x27000 |
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