Conflict Between Tgr Read And Input Capture; Figure 18.76 Conflict Between Tgr Read And Input Capture - Renesas HD6417641 Hardware Manual

Section 18 Multi-Function Timer Pulse Unit (MTU)
18.7.8

Conflict between TGR Read and Input Capture

If an input capture signal is generated in the T2 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 18.76 shows the timing in this case.
Pφ
Address
Read signal
Input capture
signal
TCNT
TGR
Buffer register

Figure 18.76 Conflict between TGR Read and Input Capture

Rev. 4.00 Sep. 14, 2005 Page 632 of 982
REJ09B0023-0400
Buffer register read cycle
T1 T2
Buffer register
address
N
M N
M