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3.2.5 Line control register
This register (LCR: 5000_0010H (UART0), 5001_0010H (UART1), 5002_0010H (UART2)) specifies the
transmission/reception data format and enables access to the divisor latch.
15
14
7
6
DLAB
Break Control
Name
R/W
Reserved
R
15:8
DLAB *
R/W
Break Control
R/W
Stick Parity *
R/W
EPS *
R/W
PEN *
R/W
CHAPTER 3 REGISTERS
13
12
5
4
Stick Parity
EPS
Bit
After Reset
0
Reserved. When these bits are read, 0 is returned for each bit.
7
0
Setting this bit to 1 enables specifying the divisor latch (DLM/DLL registers).
When this bit is set to 0 after specifying the divisor latch, access to the divisor
latch is prohibited and generation of the 16x clock according to the specified
value is started by the baud rate generator.
Caution
6
0
Controls break state generation and transmission.
The serial output (UARTx_SOUT) is forcibly set to 0 while this bit is set to 1,
and such output is canceled when this bit is set to 0. This bit directly controls
the SOUT output level but does not affect the internal circuits.
Caution
5
0
Selects the type of parity bit used to verify transmitted/received data.
The setting of this bit is valid only when a parity bit is used (bit 3 = 1).
An even, odd, or fixed value (high or low) is set by using bit 4.
0: Parity check using an even or odd parity bit
1: Parity check using a stick parity bit
4
0
Selects the odd or even parity when bit 3 is set to 1 and bit 5 is set to 0.
Selects the level of the stick parity when bit 3 and bit 5 are set to 1.
0: Odd parity / Stick High (fixed to 1)
1: Even parity / Stick Low (fixed to 0)
3
0
Specifies whether to enable the parity check.
0: No parity bit.
1: Adds a parity bit on the transmission side.
The parity bit is checked on the reception side.
User's Manual S19262EJ3V0UM
11
10
Reserved
3
2
PEN
STB
Function
The 16x clock stops after a master reset. The baud rate
generator starts generating the 16x clock when it detects the
change of this bit setting (from 1 to 0). After generation
starts, the 16x clock will not stop unless a master reset is
input.
If this bit is set to 1 during transmission, only framing errors
might be detectable on the reception side. To detect breaks
for sure, this bit must be set when transmission has
completed (the transmit buffer empty).
9
8
1
0
WLS[1:0]
(1/2)
21
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