A/D Control Register (Adcr) - Renesas F-ZTAT H8 Series Hardware Manual

Section 15 A/D Converter
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog
input channels. Clear the ADST bit to 0 before changing the channel selection.
Group
Selection Channel Selection
CH2 CH1
0 0
1
1 0
1
15.2.3

A/D Control Register (ADCR)

Bit 7
TRGE
Initial value 0
Read/Write R/W
Trigger enable
Enables or disables external triggering of A/D conversion
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7: TRGE Description
0 A/D conversion cannot be externally triggered
1 A/D conversion starts at the falling edge of the external trigger signal (ADTRG)
Bits 6 to 0—Reserved: Read-only bits, always read as 1.
Rev. 7.00 Sep 21, 2005 page 542 of 878
REJ09B0259-0700
CH0 Single Mode
0 AN (Initial value)
0
1 AN
1
0 AN
2
1 AN
3
0 AN
4
1 AN
5
0 AN
6
1 AN
7
6 5
— —
1 1
— —
Description
Scan Mode
AN
AN
AN
AN
AN
AN
AN
AN
4 3 2
— — —
1 1 1
— — —
Reserved bits
0
, AN
0 1
to AN
0 2
to AN
0 3
4
, AN
4 5
to AN
4 6
to AN
4 7
1 0
— —
1 1
— —
(Initial value)