A/D Control Register (Adcr) - Renesas H8S Series Hardware Manual

16-bit single-chip microcomputer

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Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input

Only set the input channel while conversion is stopped (ADST = 0).

A/D Control Register (ADCR)

Initial value :

Note: * Applies to the H8S/2398, H8S/2394, H8S/2392, and H8S/2390.

ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations.

ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode.

Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D

conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0).

(1) For H8S/2357 and H8S/2352

Bits 5 to 0—Reserved: They are always read as 1 and cannot be modified.

(2) For H8S/2398, H8S/2394, H8S/2392, and H8S/2390

Bits 5, 4, 1, and 0—Reserved: They are always read as 1 and cannot be modified.

Bits 3 and 2—Reserved: Should always be written with 1.

Rev.6.00 Oct.28.2004 page 544 of 1016

REJ09B0138-0600H

Channel Selection

A/D conversion start by external trigger is disabled

A/D conversion start by external trigger (TPU) is enabled

A/D conversion start by external trigger (8-bit timer) is enabled

A/D conversion start by external trigger pin (ADTRG) is enabled

Single Mode (SCAN=0)

AN0 (Initial value)

—/(R/W)* —/(R/W)*

Scan Mode (SCAN=1)

(Initial value)