A/D Control Register (Adcr) - Renesas H8S Series Hardware Manual

16.3.3

A/D Control Register (ADCR)

The ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name
7 TRGS1
6 TRGS0
5, 4 —
3 CKS1
2 CKS0
1, 0 —
Initial Value R/W
0 R/W
0 R/W
All 1 —
0 R/W
0 R/W
All 1 —
Description
Timer Trigger Select 0 and 1
Enables the start of A/D conversion by a trigger
signal. Only set bits TRGS0 and TRGS1 while
conversion is stopped (ADST = 0).
00: A/D conversion start by software is enabled
01: A/D conversion start by TPU conversion start
trigger is enabled
10: Setting prohibited
11: A/D conversion start by external trigger pin
(ADTRG) is enabled
Reserved
These bits are always read as 1.
Clock Select 0 and 1
These bits specify the A/D conversion time. The
conversion time should be changed only when
ADST = 0. Specify a setting that gives a value
within the range shown in table 21-7.
00: Conversion time = 530 states (max.)
01: Conversion time = 266 states (max.)
10: Conversion time = 134 states (max.)
11: Conversion time = 68 states (max.)
Reserved
These bits are always read as 1.
Rev. 6.00 Mar 15, 2006 page 443 of 570
Section 16 A/D Converter
REJ09B0211-0600