Noise Canceler; Figure 15.15 Receive Mode Operation Timing; Figure 15.16 Block Diagram Of Noise Conceler - Renesas H8 Series Hardware Manual

2
Section 15 I C Bus Interface 2 (IIC2)
SCL
SDA
(Input)
MST
TRS
RDRF
ICDRS
ICDRR
User
[2] Set MST
processing
(when outputting the clock)
15.4.7

Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.16 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
Rev. 1.00 Aug. 28, 2006 Page 268 of 400
REJ09B0268-0100
1 2
Bit 6
Bit 0 Bit 1
Data 1

Figure 15.15 Receive Mode Operation Timing

Sampling clock
C
D Q
Latch
System clock
period

Figure 15.16 Block Diagram of Noise Conceler

7 8 1
Bit 7 Bit 0
Data 2
Data 1
[3] Read ICDRR
C
D Q
March detector
Latch
7 8 1
Bit 6 Bit 7 Bit 0 Bit 1
Data 3
Data 2
[3] Read ICDRR
Internal
SCL or SDA
signal
2