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17.4.6
Noise Canceler
The logic levels at the SCL and SDA pins are latched internally via the noise canceler. Figure
17.13 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches match. If they do not match, the previous value is retained.
SCL or SDA
input signal
Sampling
clock
17.4.7
Example of Use
Flowcharts in respective modes that use the I
Rev. 1.00, 09/03, page 500 of 704
Sampling clock
C
D
Q
D
Latch
System clock
cycle
Figure 17.13 Block Diagram of Noise Canceler
2
C
Q
Match detector
Latch
C bus interface are shown in figures 17.14 to 17.17.
Internal
SCL or SDA
signal
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