Noise Canceler; Table 17.9 Examples Of Operation Reservation Adapter Operation Using Dtc - Renesas H8S/2158 User Manual

Table 17.9 Examples of Operation Reservation Adapter Operation Using DTC

Master Transmit
Item Mode
Slave address + Transmission by
R/W bit CPU (ICDRX +
transmission/ ICCMD write)
reception
Dummy data —
read
Actual data Transmission by
transmission/ DTC (ICDRX
reception write)
Dummy data —
(H'FF) write
Last frame Not necessary
processing
Transfer MTREQ: Clearing
request by CPU
processing after
CREQ: Clearing
last frame
by CPU
processing
Setting of Transmission:
number of DTC Actual data count
transfer data
frames
17.5.8

Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 17.17 shows a block diagram of the noise canceler.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) pin
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Master Receive Slave Transmit
Mode Mode
Transmission by Not necessary
CPU (ICDRX +
ICCMD write)
Processing by —
CPU (ICDRX
read)
Reception by Transmission by
DTC (ICDRX DTC (ICDRX
read) write)
— Not necessary
Not necessary Not necessary
MRREQ: Clearing STREQ: Clearing
by CPU by CPU
CREQ: Clearing CREQ: Clearing
by CPU by CPU
Reception: Actual Transmission:
data count Actual data
Rev. 3.00 Jan 25, 2006 page 533 of 872
2
Section 17 I C Bus Interface (IIC)
Slave Receive
Mode
Not necessary
—
Reception by DTC
(ICDRX read)
—
Not necessary
SRREQ: Clearing
by CPU
CREQ: Clearing
by CPU
Reception: Actual
data count
REJ09B0286-0300