Noise Canceler; Example Of Use; Figure 15.13 Block Diagram Of Noise Canceler - Renesas H8S/2368 Series Hardware Manual

15.4.6

Noise Canceler

The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.13 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
SCL or SDA
input signal
Sampling
clock
15.4.7

Example of Use

Flowcharts in respective modes that use the I
Sampling clock
C
D Q D
Latch
System clock
period

Figure 15.13 Block Diagram of Noise Canceler

C
Q
March detector
Latch
2
C bus interface are shown in figures 15.14 to 15.17.
Rev. 2.00, 05/03, page 611 of 820
Internal
SCL or SDA
signal