Noise Canceler; Figure 9.9 Noise Canceler Block Diagram - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Bit 3: Timer G module standby mode control (TGCKSTP)

Bit 3 controls setting and clearing of module standby mode for timer G.

Timer G is set to module standby mode

Timer G module standby mode is cleared

Noise Canceler

The noise canceler consists of a digital low-pass filter that eliminates high-frequency component

noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in

Figure 9.9 shows a block diagram of the noise canceler.

Input capture

input signal

Sampling clock

∆t: Set by CKS1 and CKS0

The noise canceler consists of five latch circuits connected in series and a match detector circuit.

When the noise cancellation function is not used (NCS = 0), the system clock is selected as the

sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the

internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the

rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If

all the outputs do not match, the previous value is retained. After a reset, the noise canceler output

is initialized when the falling edge of the input capture input signal has been sampled five times.

Rev. 6.00 Aug 04, 2006 page 301 of 680

Section 9 Timers

(initial value)

REJ09B0145-0600