Interrupt Vector Tables; Fixed Vector Tables - Renesas M16C Series User Manual

M30240 Group
• A-D conversion interrupt
This is an interrupt that the A-D converter generates.
• UART0, UART1 and UART2 transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1 and UART2 reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through Timer A4 interrupt
These are interrupts that Timer A generates
• Timer B0 interrupt and Timer B1 interrupt
These are interrupts that Timer B generates.
• INT0 interrupt and INT1 interrupt
An INT interrupt occurs if either a rising edge or a falling edge is input to the INT pin. The edge polarity is se-
lected by using the polarity select bit.

4.1.2 Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector
table. Set the first address of the interrupt routine in each vector table. Two types of interrupt vector
tables are available — fixed vector table in which addresses are fixed and variable vector table in which
addresses can be varied by the setting.

4.1.2.1 Fixed vector tables

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area
extending from FFFDC
the interrupt routine in each vector table. Table 4.1 shows the interrupts assigned to the fixed vector
tables and addresses of the vector tables.
Table 4.1: Interrupts assigned to the fixed vector tables and addresses of vector tables
Interrupt source
Undefined instruction
Overflow
BRK instruction
Address match
Single step (Note)
Watchdog timer
DBC (Note)
NMI
Reset
Note: Interrupts used for debugging purposes only.
Rev.1.00 Sep 24, 2003 Page 332 of 360
to FFFFF . One vector table comprises four bytes. Set the first address of
16 16
Vector table addresses
Address (L) to Address (H)
FFFDC to FFFDF
16 16
FFFE0 to FFFE3
16 16
FFFE4 to FFFE7
16 16
FFFE8 to FFFEB
16 16
FFFEC to FFFEF
16 16
FFFF0 to FFFF3
16 16
FFFF4 to FFFF7
16 16
FFFF8 to FFFFB
16 16
FFFFC to FFFFF
16 16
Overview of Interrupts
Remarks
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector contains FF16, program execution starts
from the address shown by the vector in the variable
vector table.
There is an address-match interrupt enable bit
Do not use
Do not use
External interrupt by input to NMI pin