Reset State - Renesas H8S/2319 series Hardware Manual

Bus-released state
Exception-handling state
RES = high

Reset state

From any state except hardware standby mode, a transition to the reset state occurs whenever RES
Notes: 1.
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
2.
2.8.2 Reset State
When the RES input goes low all current processing stops and the CPU enters the reset state. All
interrupts are masked in the reset state. Reset exception handling starts when the RES signal
changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 11,
Watchdog Timer.
Rev. 5.00, 12/03, page 60 of 1088
End of bus request
Program execution
End of bus
request
Bus
request
Request for
End of
exception
exception
handling
handling
External interrupt
STBY = high, RES = low
*1
Figure 2-12 State Transitions
Bus request
state
SLEEP
instruction
with
SLEEP
SSBY = 0
instruction
with
SSBY = 1
Interrupt
request
Software standby mode
Hardware standby mode
Sleep mode
*2
Power-down state