Reset State - Renesas H8S/2633 Series Hardware Manual

Bus-released state
Exception handling state
MRES= High
Manual reset state *

Reset state *1

Notes: *1 From any state except hardware standby mode, a transition to the power-on reset state occurs whenever RES
goes low. From any state except hardware standby mode and power-on reset mode, a transition to the manual
reset state occurs whenever MRES goes low. A transition can also be made to the reset state when the
watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when STBY goes low.
*2
Apart from these states, there are also the watch mode, subactive mode, and the subsleep mode.
*3
See section 24, Power-Down States.
2.8.2 Reset State
The CPU enters the reset state when the RES pin goes low, or when the MRES pin goes low while
manual resets are enabled by the MRESE bit. In the reset state, currently executing processing is
halted and all interrupts are disabled.
For details of MRESE bit setting, see section 3.2.2, System Control Register (SYSCR).
Reset exception handling starts when the RES or MRES pin* changes from low to high.
The reset state can also be entered in the event of watchdog timer overflow. For details see section
15, Watchdog Timer.
Note: * MRES pin in the case of a manual reset.
86
End of bus request
Bus request
Program execution state
External interrupt request
RES= High
Power-on reset state *
1
Figure 2-15 State Transitions
Sleep mode
Software standby mode
STBY= High, RES= Low
1
Hardware standby mode*
Power-down state*
2
3