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M
1
6
C
2 /
6
A
G
o r
u
p
(
M
1
6
9.4.3 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
9.4.3.1 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Address
MSB
m – 4
m – 3
m – 2
m – 1
m
Content of previous stack
Content of previous stack
m + 1
Stack status before interrupt request
is acknowledged
Figure 9.4.3.1. Stack Status Before and After Acceptance of Interrupt Request
R
e
. v
2
0 .
0
F
e
b
1 .
, 5
2
0
0
7
R
E
J
0
9
B
0
2
0
2
0 -
2
0
0
C
2 /
6
, A
M
1
6
C
2 /
6
, B
M
1
6
Stack
LSB
[SP]
SP value before
interrupt request is
accepted.
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f o
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Address
MSB
m – 4
m – 3
m – 2
m – 1
m
Content of previous stack
Content of previous stack
m + 1
Stack status after interrupt request
is acknowledged
Stack
LSB
PC
L
PC
M
FLG
L
FLG
PC
H
H
9. Interrupt
[SP]
New SP value
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