Timer Counter (Tcnt); Timer General Register (Tgr); Timer Start Register (Tstr) - Renesas H8S Series Hardware Manual

10.3.6

Timer Counter (TCNT)

The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
10.3.7

Timer General Register (TGR)

The TGR registers are dual function 16-bit readable/writable registers, functioning as either output
compare or input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3
and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be
designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units;
they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–
TGRC and TGRB–TGRD.
10.3.8

Timer Start Register (TSTR)

TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5.
When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT
counter.
Bit Bit Name Initial value
7, 6 — All 0
5 CST5 0
4 CST4
3 CST3
2 CST2
1 CST1
0 CST0
Section 10 16-Bit Timer Pulse Unit (TPU)
R/W Description
— Reserved
Only 0 should be written to these bits.
R/W Counter Start 0 to 5
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained.
If TIOR is written to when the CST bit is cleared to 0,
the pin output level will be changed to the set initial
output value.
0: TCNT_0 to TCNT_5 count operation is stopped
1: TCNT_0 to TCNT_5 performs count operation
Rev. 6.00 Mar 15, 2006 page 195 of 570
REJ09B0211-0600