Interrupt Operation; Dma Support - Renesas M16C/29 Series Hardware Manual

M16C/29 Group

13.2 Interrupt Operation

The IC/OC interrupt contains several request causes. Figure 13.2.1 shows the IC/OC interrupt block dia-
gram and Table 13.2.1 shows the IC/OC interrupt assignation.
When either the base timer reset request or base timer overflow request is generated, the IR bit (bit 3 in the
BTIC register) corresponding to the IC/OC base timer interrupt is set to "1" (with an interrupt request). Also
when an interrupt request of each eight channels (channel i) is generated, the bit i in the G1IR register is set
to "1" (with an interrupt request). At this time, if the bit i in the G1IE0 register is "1" (IC/OC interrupt 0 request
enabled), the IR bit (bit 3 in the ICOC0IC register) corresponding to the IC/OC interrupt 0 is set to "1" (with
an interrupt request). And if the bit i in the G1IE1 register is "1" (IC/OC interrupt 1 request enabled), the IR
bit (bit 3 in the ICOC1IC register) corresponding to the IC/OC interrupt 1 is set to "1"(with an interrupt
request).
Additionally, because each bit in the G1IR register is not automatically set to "0" even if the interrupt is
acknowledged, set to "0" using a program. If these bits are left "1", all IC/OC channel interrupt causes,
which are generated after setting the IR bit to "1", will be disabled.
Interrupt Select Logic
Channel 0 to 7 Interrupt requests
All register are read / write
Base timer reset request
Base timer overflow request
Figure 13.2.1. IC/OC Interrupt and DMA request generation
Table 13.2.1. Interrupt Assignment
Interrupt
IC/OC base timer interrupt
IC/OC interrupt 0
IC/OC interrupt 1

13.3 DMA Support

Each of the interrupt sources - the eight IC/OC channel interrupts and the one Base Timer interrupt - are
capable of generating a DMA request.
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
G1IE0
ENABLE
Interrupt control register
BTIC(0047
ICOC0IC(0045
ICOC0IC(0046
page 149 of 402
13. Timer S (Input Capture / Output Compare)
DMA Requests (channel 0 to 7)
G1IR G1IE1
REQUEST ENABLE
Base Timer Interrupt / DMA Request
)
16
)
16
)
16
IC/OC interrupt 1 request
IC/OC interrupt 0 request
IC/OC base timer interrupt request