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4.2 FIFOs
4.2.1 Operation in FIFO interrupt mode
The following interrupts occur while the receive FIFO interrupt is enabled (when bit 0 of the FCR register, bit 0 of
the IER register, and bit 2 of the IER register are set to 1).
When the amount of data in the receive FIFO reaches the trigger level, a receive data enable interrupt is issued.
When the amount of data in the receive FIFO becomes less than the trigger level, the interrupt is cleared.
The received data available interrupt is indicated in the IIR register when the receive FIFO reaches the trigger
level.
A receiver line status interrupt (IIR = 06H) has a higher priority than the received data available interrupt (IIR =
04H).
When a character is transmitted to the receive FIFO from the receive shift register (RSR), bit 0 (DR) of the LSR
register is set to 1. When the receive FIFO empties, the DR bit is cleared.
4.2.2 Operation in FIFO polled mode
When the FIFO is enabled (bit 0 of the FCR register = 1), bits 3 to 0 of the IER register are set to 0 in FIFO polled
mode. Transmission and reception can then be set to FIFO polled mod separately.
In this mode, the user program checks the transmission and reception status by using the LSR register.
The immediately preceding statuses are:
Bit 0 of the LSR register is set to 1 when at least 1 byte is stored in the receive FIFO.
Bits 4 to 1 of the LSR register indicate details about the error occurrence.
Bit 5 of the LSR register indicates that the THR is empty.
Bit 6 of the LSR register indicates that both THR and TSR are empty.
Bit 7 of the LSR register indicates whether the receive FIFO contains some errors.
4.2.3 Read when the receive FIFO is empty
If the receive FIFO is read while it is empty, the read counter is not incremented.
In this case, a receive FIFO underrun error is detected (bit 7 of HCR2 register).
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CHAPTER 4 DESCRIPTION OF FUNCTIONS
User's Manual S19262EJ3V0UM
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