Clearing Watch Mode; Oscillator Settling Time After Watch Mode Is Cleared; Notes On External Input Signal Changes Before/After Watch Mode; Subsleep Mode - Renesas F-ZTAT H8 Series Hardware Manual

5. Power-Down Modes
5.4.2

Clearing Watch Mode

Watch mode is cleared by an interrupt (timer A, IRQ
pin.
Clearing by Interrupt: Watch mode is cleared when an interrupt is requested. The mode to which
a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both
LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and
MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive
mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2–STS0 has
elapsed, a stable clock signal is supplied to the entire chip, and interrupt exception handling starts.
Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in
the interrupt enable register.
Clearing by RES Input: Clearing by RES pin is the same as for standby mode; see section 5.3.2,
Clearing Standby Mode.
5.4.3

Oscillator Settling Time after Watch Mode Is Cleared

The waiting time is the same as for standby mode; see section 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
5.4.4

Notes on External Input Signal Changes before/after Watch Mode

See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
5.5

Subsleep Mode

5.5.1

Transition to Subsleep Mode

The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1.
In subsleep mode, operation of on-chip peripheral modules other than timer A, timer C*, and the
LCD controller is halted. As long as a minimum required voltage is applied, the contents of CPU
registers and some registers of the on-chip peripheral modules, and the on-chip RAM contents, are
retained. I/O ports keep the same states as before the transition.
Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854
Group.
Rev.3.00 Jul. 19, 2007 page 112 of 532
REJ09B0397-0300
) or by a input at the RES
, WKP to WKP
0 0 7