Sleep Mode; Transition To Sleep Mode - Renesas H8/3847R Series Hardware Manual

8-bit single-chip microcomputer super low power

Table of Contents

Section 5 Power-Down Modes

Bits 1 and 0: Subactive mode clock select (SA1 and SA0)

These bits select the CPU clock rate (φ

cannot be modified in subactive mode.

* Don't care

Sleep Mode

1. Transition to Sleep (High-Speed) Mode

The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is

executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON

bits in SYSCR2 are also cleared to 0. In sleep mode CPU operation is halted but the on-chip

peripheral functions. CPU register contents are retained.

2. Transition to Sleep (Medium-Speed) Mode

The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is

executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2

is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in

sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are

operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and

MA0 bits in SYSCR1. CPU register contents are retained.

The CPU may operate at a 1/2 state faster timing at transition to sleep (medium-speed) mode.

Rev. 6.00 Aug 04, 2006 page 138 of 680

REJ09B0145-0600

/8) in subactive mode. SA1 and SA0

(initial value)