Sleep Mode; Transition To Sleep Mode; Clearing Sleep Mode - Renesas F-ZTAT H8 Series Hardware Manual

Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0): These bits select the CPU clock rate
/2, φ /4, or φ
(φ /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode.
W W W
Bit 1: SA1 Bit 0: SA0
0 0
1
1 *
Legend: * Don't care
5.2

Sleep Mode

5.2.1

Transition to Sleep Mode

The system goes from active mode to sleep mode when a SLEEP instruction is executed while the
SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU
operation is halted but the on-chip peripheral functions other than PWM* are operational. The
CPU register contents are retained.
Note: * This is a function of the H8/3857 Group only, and is not provided in the H8/3854
Group.
5.2.2

Clearing Sleep Mode

Sleep mode is cleared by an interrupt (timer A, timer B, timer C*, timer F, IRQ
IRQ , IRQ , WKP to WKP
3 4 0
Note: * The timer C, SCI1, and IRQ
are not provided in the H8/3854 Group.
Clearing by Interrupt: When an interrupt is requested, sleep mode is cleared and interrupt
exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in
SYSCR2, or active (medium-speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
Clearing by RES Input: When the RES pin goes low, the CPU goes into the reset state and sleep
mode is cleared.
Description
φ
/8
W
φ
/4
W
φ
/2
W
, SCI1*, SCI3, A/D converter) or by input at the RES pin.
7
interrupts are functions of the H8/3857 Group only, and
2
5. Power-Down Modes
0
Rev.3.00 Jul. 19, 2007 page 107 of 532
(initial value)
, IRQ , IRQ *,
1 2
REJ09B0397-0300