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M30245 Group
3.6 CRC Calculation SFR Access Snoop Function in Clock Synchronous Serial Data Transmit
Overview
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Specifications
Operation
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
The M30245 group, by use of DMAC, transfers data from the internal RAM to the UART1 and the
result is transferred to the UART1 by use of SFR access snoop function. The block diagram is
shown in Figure 3.6.1 and the setting routine is shown in Figure 3.6.2 to Figure 3.6.4.
The peripheral functions to be used are as follows:
• DMAC 1 Channel
• Internal RAM (address 00400
• UART1 (Clock synchronous serial I/O mode)
• CRC calculation circuit
• SFR access snoop function
(1) Data transfer is performed starting at address 00400
UART1. Data are transferred from area between the address 00400
the UART1. Transfer is executed every time 1 byte of serial transmit is completed.
(2) Use the DMA0 to transfer data from the internal RAM to the UART1. Select the UART1
transmit to the DMA0 request factor. Select the single transfer mode and set the DMA0
transfer counter to 511 bytes (512-1).
(3) Set the CRC calculation circuit to the CRC-CCITT and set CRC snoop address register to the
address of UART1 transmit buffer register (write snoop).
(4) On completing the DMA, 2-byte data of CRC data register (calculation result) are transferred
to the UART1 and operation is completed.
(1) Initialize the UART1 related registers.
(2) Initialize the DMA0 related registers in DMA disable state.
(3) Set the DMA0 transfer counter to the transfer data consisting of 511 bytes (in this case, 8-bit
transfer).
(4) Initialize the CRC calculation circuit and the SFR access snoop function.
(5) Set the software DMA request bit of DMA0 to "1". At this time, 1st byte data are transferred
from RAM to the transmit buffer of the UART1. Simultaneously, the transfer source address
is incremented and the content of the transfer counter is down-counted. The transferred data
are automatically written in CRC input register by the SFR access snoop function.
(6) When the transmit buffer of the UART1 becomes writable state, the DMA transfer request is
occurred by the UART1. At this time, the next data are transferred from RAM to the transmit
buffer of the UART1. Simultaneously, the transfer source address is incremented and the
content of the transfer counter is down-counted. The transferred data are automatically writ-
ten in CRC input register by the SFR access snoop function.
(7) As a result of repetition of the above (6), when the DMA0 transfer counter underflow, DMA
enable bit is set to "0" to complete the DMA0 transfer. Simultaneously, the DMA0 interrupt
request occurs. When the DMA0 interrupt request is detected, CRC data register (2 bytes) is
read, it is transferred to the UART1 transmit buffer sequentially.
page 311 of 354
) 512 bytes
16
3. CRC Snoop Function Applications
from the area with 512 bytes to the
16
and the 512nd byte to
16
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