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NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or
disable pulse output on a bit-by-bit basis. However, the H8S/2633 Series has no output pins
corresponding to NDRL.
Bits 7 to 0
NDER7 to NDER0
0
1
12.2.2
Output Data Registers H and L (PODRH, PODRL)
PODRH
Bit
:
7
POD15
Initial value :
0
R/W
:
R/(W)*
PODRL
Bit
:
7
POD7
Initial value :
0
R/W
:
R/(W)*
Note: * A bit that has been set for pulse output by NDER is read-only.
PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse
output. However, the H8S/2633 Series has no pins corresponding to PODRL.
608
Description
Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not
transferred to POD7 to POD0)
Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to
POD7 to POD0)
6
5
POD14
POD13
0
0
R/(W)*
R/(W)*
6
5
POD6
POD5
0
0
R/(W)*
R/(W)*
4
3
POD12
POD11
POD10
0
0
R/(W)*
R/(W)*
R/(W)*
4
3
POD4
POD3
POD2
0
0
R/(W)*
R/(W)*
R/(W)*
(Initial value)
2
1
0
POD9
POD8
0
0
0
R/(W)*
R/(W)*
2
1
0
POD1
POD0
0
0
0
R/(W)*
R/(W)*
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