Ss Transmit Data Registers 0 To 3 (Sstdr0 To Sstdr3) - Renesas H8SX/1520 Series Hardware Manual

Bit Bit Name

1, 0
14.3.7

SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)

SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid. Be
sure not to access invalid SSTDRs
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
Downloaded from Elcodis.com electronic components distributor
Initial
Value R/W
All 0 R/W
7 6 5
0 0 0
R/W R/W R/W
7 6 5
0 0 0
R/W R/W R/W
7 6 5
0 0 0
R/W R/W R/W
7 6 5
0 0 0
R/W R/W R/W
Section 14 Synchronous Serial Communication Unit (SSU)
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
4 3
0 0
R/W R/W
4 3
0 0
R/W R/W
4 3
0 0
R/W R/W
4 3
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 523 of 804
2 1 0
0 0 0
R/W R/W R/W
2 1 0
0 0 0
R/W R/W R/W
2 1 0
0 0 0
R/W R/W R/W
2 1 0
0 0 0
R/W R/W R/W
REJ09B0104-0300